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Seeking a Principal Design and Verification Engineer to join a team supporting classified government programs.
Active Secret clearance required due to the nature of the work (Active Secret clearance requires US Citizenship)
Burlington, MA – Onsite
Responsibilities and Requirements
- The Principal Design Engineer will plan, architect, and develop configurable, self-checking test benches in System Verilog/UVM and/or VHDL
- Develop constrained-random, metric-driven test plans and strategies to verify FPGAs used in Electronic Warfare systems
- Collect and analyze coverage metrics to improve test case effectiveness
- The Design Engineer will create reusable Verification IP for use across the organization
- Lead and mentor Design Verification teams
- Collaborate with subject matter experts to enhance verification approaches and broaden Electronic Warfare domain knowledge
- Mentor and support junior engineers across multiple locations
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field (STEM) and 10+ years of relevant experience
- Active Secret Clearance
- Proficiency with FPGA/ASIC design and verification tools (Mentor Questa or Cadence)
- Experience developing and implementing verification test plans
- Preferred experience in Digital Signal Processing (DSP)
- Familiarity with MATLAB/Simulink
